The disclosed embodiments of the present invention relate to converting an input signal in a digital domain into an output signal in an analog domain, and more particularly, to a digital-to-analog conversion apparatus for generating a combined analog output by combining analog outputs derived from using different sampling clocks and a related method thereof.
A digital-to-analog converter (DAC) is used to convert a discrete digital input data into a continuous analog output, and is widely used in a variety of applications. However, since the DAC converts the discrete sampling digital impulse data to the continuous analog waveform, the continuous analog output of a DAC is more typically a zero-order hold series of stair steps. This transformation from discrete sampling impulse to continuous stair steps will induce the high frequency image signal. If the digital output signal frequency is Fo, and the sampling frequency is Fs, these images are located at N*Fs+M*Fo, where N=1, 2, 3, . . . and M=+/−1, and have no external filtering image amplitude roll-off as sin(x)/x where x=pi*Fo/Fs. Thus, it is required to alleviate/eliminate the undesired images to prevent other circuit elements from being affected by the undesired images. One possible solution is to use a higher-order post-DAC filter for offering good image rejection. However, such a design would increase the production cost inevitably. Another possible solution is to increase the sampling frequency of the DAC to move the undesired images to higher frequencies for allowing the use of a lower-order post-DAC filter to remove the undesired images. However, such a design is not easy to be implemented when sampling frequency is more than several hundred million hertz.
Thus, there is a need for an innovative DAC system which is capable of offering good image rejection while using a lower-order post-DAC filter.